ASSIGNMENT

Assignment–1

Q1. Explain the internal structure of CPLD. How the output is considered to be the registered output?

Q2. What are the classical techniques for reducing the complexity of IC design? Explain each of them.

Q3. Compare VLSI Design Style with FPGA and CPLD?

Q4. Explain complete VLSI Design flow with all domains.

Q5. Explain the FPGA.

Q6. Explain the CPLD.

Q7. Explain the design hierarchy concept of regularity, modularity and locality.

Assignment-2

Q1. Draw the stick diagram of CMOS inverter.

Q2. What are the reasons behind different design rules in layout.

Q3. Draw the symbolic layout of a 2-input NOR gate.

Q4. Explain basic steps for fabrication of CMOS

Q5. Calculation of resistance and capacitance.

Q6. Explain the Layout design rules.

Q7. Explain fabrication process of PMOS & Bi-CMOS

Assignment-3

Q1. Draw the three transistor dynamic RAM cell also. Draw the Stick diagram for the same using CMOS Technology.

Q2. Explain the ROM Designing techniques with different symbolic layouts.

Q3. Prepare a stick diagram for 4:1 multiplexer. Using N-MOS switches

Q4. Explain CMOS Stick diagram for parity generator.

Q5. Explain PLA Decoder.

Q6. Explain the combinational & Sequential logic.

Q7. Explain the comparator.

Q8. Explain the 4-bit Adder.

Assignment-4

Q1. Explain blocking & non-blocking assignments in Verilog with suitable examples.

Q2. Explain operators and data types.

Q3. Explain the case statement with all variation in Verilog.

Q4. What is procedure? Explain with example.

Q5. Explain the CAD Tools.

Q6. Explain the component in VHDL and Verilog.

Q7. Explain the power dissipation in logic gates entity.

Q8. Explain the Signal Architecture.

Q9. Explain the operators, data types, generic, loop, data flow, structural and Behavioral.

Assignment-5

Q1. Explain block statement in VHDL?

Q2. What is test bench synthesis? Explain some waveform patterns.

Q3. Explain bus structure in VHDL?

Q4. Explain delays in VHDL.

Q5. Explain operator overloading.

Q6. Explain power dissipation in logic gates entity.

Q7. Explain delays & verifications in VHDL.

Q8. Explain the Verilog FSM.