Previous Year Question Paper
ASSIGNMENT
Assignment–1 Q1. Explain the internal structure of CPLD. How the output is considered to be the registered output? Q2. What are the classical techniques for reducing the complexity of IC design? Explain each of them. Q3. Compare VLSI Design Style with FPGA and CPLD? Q4. Explain complete VLSI Design flow with all domains. Q5. Explain the FPGA. Q6. Explain the CPLD. Q7. Explain the design hierarchy concept of regularity, modularity and locality. Assignment-2 Q1. Draw the stick diagram of CMOS inverter. Q2. What are the reasons behind different design rules in layout. Q3. Draw the symbolic layout of a 2-input NOR gate. Q4. Explain basic steps for fabrication of CMOS Q5. Calculation of resistance and capacitance. Q6. Explain the Layout design rules. Q7. Explain fabrication process of PMOS & Bi-CMOS Assignment-3 Q1. Draw the three transistor dynamic RAM cell also. Draw the Stick diagram for the same using CMOS Technology. Q2. Explain the ROM Design...
Comments
Post a Comment